With trends toward high integration of semiconductor devices and micro-miniaturization of a design rule in recent years, for a silicon wafer to be used as a substrate thereof, it is required that no void defects such as Crystal Originated Particle (COP) are present in a region near the wafer surface to be a device active region (specially from the wafer surface to a depth of 5 μm, hereinafter also referred to as a surface region).
Generally, a silicon wafer made by slicing a silicon single crystal ingot grown by a CZ method and then mirror polishing has void defects such as COP therein. The void defects such as COP in the device active region can be eliminated, for example, by subjecting the silicon wafer to heat treatment at a temperature of 1100° C. or higher in an Ar gas atmosphere for 30 minutes or longer by use of a vertical type heat-treatment apparatus or the like (for example, Patent Document 1).
Also, such a silicon wafer having no void defects can be produced, for example by controlling V/G (V indicates a pulling rate and G indicates a temperature gradient) when growing the silicon single crystal ingot in the CZ method, pulling up the silicon single crystal ingot entirely having a defect-free region and then slicing the ingot (For example, Patent Document 2).
However, in the method described in Patent Document 2, the void defects can be generated by a slight variation in V/G and it is very difficult to control it. In addition, in the case of pulling up the defect-free region by controlling V/G, generally, the pulling rate V is required to be lowered and thus productivity in growing the silicon single crystal becomes lower.
For these reasons, a method for forming a defect free layer in the wafer surface region where the device is formed is proposed (for example in Patent Document 3). The method includes growing a silicon single crystal ingot having a region where vacancy type point defects predominate (hereinafter referred to as V-rich region) so that the pulling rate V can be raised; subjecting a silicon wafer obtained by slicing the single crystal ingot to an HF treatment and thereby removing an inner-wall oxide film of a void defect present in the wafer surface region; and then subjecting the silicon wafer to a rapid heating/cooling thermal process (hereinafter also referred to as RTP).
On the other hand, a silicon wafer having highly dense BMD (Bulk Micro Defect) in a region deeper than the wafer surface region (specially, a region deeper than 5 μm from the wafer surface, hereinafter referred to as a wafer bulk region) has a gettering effect for metal impurities or the like incorporated during a device process.
In this respect, for example, a method of performing RTP in a nitrogen or inert atmosphere and controlling the cooling rate, thereby allowing excess vacancies to remain in the wafer bulk region and forming oxygen precipitate nuclei is proposed (For example, Patent Documents 4 and 5).
Further, a method of forming a thermal oxide film having a thickness that is preselected to correspond to a preselected depth of defect-free region in an oxidation atmosphere when performing RTP (for example, Patent Document 6) and a method of performing RTP by supplying an argon-based gas to the silicon wafer surface side and a nitrogen-based gas to the back surface side (for example, Patent Document 7) are known.
As an apparatus for performing such RTP, for example, such apparatus that includes a chamber for accommodating a substrate; a substrate support member arranged in the chamber and having a ring frame for supporting the edge portion of the substrate; a heating portion for heating the substrate; and a modifying gas supplying portion for supplying a modifying gas including a first gas containing an oxide atom in the molecule and a second gas as a dilution gas into a substantially closed space formed on a back surface side of a substrate surface where a semiconductor device is formed, is effective (for example, Patent Document 8).